Avaliação e testes de heurísticas para otimização de sistemas digitais

Abstract

This work was developed to interact through an intermediate code, with a framework of synthesis of electronic systems in high level of abstraction in order to optimize combina tional circuits. The framework can be classified as a CAD (Computer Assisted Design) tool that interprets optimizes and translates digital circuits represented in schematic di agram for hardware description language representation. This work works exclusively in the part of refinement where a Genetic Algorithm implementation is used, focusing on the minimization of circuits considering its cost of production. For the development of the Algorithm, we used implementation techniques and test cases adopted from other works, such as parity and comparator function. The results were compared with the objective of evaluating the efficiency of the Algorithm also in relation to the results obtained by two traditional methods of the bibliography that use boolean algebra for minimization, which are Karnaugh and Quine-McCluskey maps. The Genetic Algorithm was effective in most of the test cases and the main disadvantage of this approach was the poor temporal performance.